The invention is in the field of Semiconductor-On-Insulator (SOI) devices, and relates more specifically to lateral thin-film SOI devices such as MOSFETS and diodes suitable for high-voltage and power applications.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, conduction losses and manufacturing simplicity and reliability. Frequently, improving one parameter, such as a breakdown voltage, will result in the degradation of another parameter, such as conduction losses. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational and fabrication drawbacks.
Improvements over the basic SOI structure, in which increased breakdown voltages are achieved by providing a linear doping profile in the drift region, are shown in U.S. Pat. No. 5,246,870 and U.S. Pat. No. 5,300,448, both commonly owned with the instant application and incorporated herein by reference. In these SOI devices, the drift region between the channel and drain in a lateral MOS structure is provided with a linear lateral doping density profile, which results in substantially increased breakdown voltage characteristics. Additionally, in U.S. Pat. No. 5,246,870, a top field plate is provided over a field oxide of essentially constant thickness to permit twice the conducting charge to be placed in the drift region, thereby reducing conduction losses without reducing breakdown voltage. However, to maintain high breakdown voltage, the total amount of conduction charge near the source side of the drift region must be kept very small, thereby leading to a bottleneck for current flow and preventing optimum reduction in conduction losses.
Another approach is taken in U.S. Pat. No. 4,247,860, incorporated herein by reference, in which a Silicon-On-Sapphire (SOS) structure employs a graded field oxide in combination with a uniform lateral doping profile to achieve enhanced high-voltage operation. This technique is useful in SOS devices, where the bottom insulating layer of sapphire is several orders of magnitude thicker than the comparable layer in SOI devices SOI that voltages from below the drift region have substantially no influence on device operation, but is not applicable to SOI devices where the buried insulating layer thickness is comparable to that of the top oxide layer and the drift region charge couples to both the top field plate and the substrate, which serves as a bottom field plate. In SOS devices, to the contrary, voltages from below the drift region have no influence, due to the thickness of the bottom insulating layer, so that the drift region charge couples only to the top field plate.
Accordingly, it would be desirable to have a lateral thin-film SOI device as described above but in which conduction losses can be further reduced without reducing the breakdown voltage of the device.